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october 2011 doc id 18349 rev 1 1/24 24 ST7590 narrow-band ofdm power line networking prime compliant system-on-chip features fully integrated narrow-band power line networking system-on-chip high performing dsp engine with embedded turn-key firmware for orthogonal frequency division multiplexing (ofdm) modulation, featuring: ? 96 sub-carriers in cenelec a band ? bdpsk, qdpsk, 8dpsk programmable modulations ? programmable bit rate up to 128 kbps ? convolutional coding and viterbi decoding ? signal to noise ratio and channel quality estimation ? full prime compliant phy on chip peripherals: ? host controller uart/spi interface ? i2c/spi external data memory interface ? high speed sram controller for optional external sram program code execution ? watchdog timer on chip 128 bit aes encryption hw block fully integrated analog front end: ? adc and dac ? high sensitivity receiver ? high linearity transmitter with intelligent gain control fully integrated power line driver ? up to 1 arms, 14 vpp single ended ? configurable active filtering topology ? ultra low distortion ? embedded temperature sensor ? current control 3.3 v or 5 v i/o digital i/o supply integrated 5 v and 1.8 v linear regulators for afe and digital core supply 8 v to 18 v line driver power supply suitable for applicat ions compliant with en50065 and fcc part 15 specifications -40 c to +85 c temperature range qfn48 7x7 (ST7590) and tqfp 100 14x14 (ST7590t) exposed pad package options application prime compliant smart metering and smart grid applications. description ST7590 is the first complete narrowband ofdm power line communication system-on-chip made using a multi-power technology with state of the art vlsi cmos lithography. the ST7590 is based on dual core architecture to assure outstanding communication performance with a very high level of flexibility and programmability for either open standard or fully customized implementations. qfn-4 8 (7 x 7 mm) 41&0 www.st.com
contents ST7590 2/24 doc id 18349 rev 1 contents 1 device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 analog front end (afe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 reception path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2 transmission path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3 power amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.4 thermal shutdown and temperature control . . . . . . . . . . . . . . . . . . . . . . . 15 4.5 zero-crossing detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.6 one time programmable (otp) memory array . . . . . . . . . . . . . . . . . . . . . 16 4.7 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.8 clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
ST7590 device description doc id 18349 rev 1 3/24 1 device description ST7590 is available in two different package options: tqfp100 and qfn48. in the tqfp100 package option, order code ST7590t, the device comes with a dedicated fw implementing prime compliant phy protocol layer and a boot loader procedure that enables the ic to boot prime mac, prime cl432 convergence layer and iec 61334-4- 32 llc layer from an external serial nv memory connected through spi interface. in the qfn 48 package option, ST7590 comes with a dedicated fw implementing the full prime protocol stack (phy, mac and convergence layer), so without the need for external memories to run the protocol. the on-chip analog front end, featuring analog to digital and digital to analog conversion and automatic gain control, plus the integrated power amplifier delivering up to 1 arms (typical) output current, makes the ST7590 the first complete narrowband ofdm power line communication system-on-chip ideal for prime compliant applications. an hw 128-bit aes encryption block with prime compliant management is available on chip when secure communication is requested. line coupling network design is also extremely si mplified, leading to a very low cost bill of material. safe operations are assured while keeping power consumption and distortion levels very low, so making ST7590 an ideal platform for the most stringent application requirements and regulatory standards compliance. figure 1. ST7590 block diagram ouptut current control thermal management p_rom x-ram y-ram dsp engine hardware accelerators line driver phy processor gain bpf bpf adc pga dac prog rom otp 8051 core uart/spi0 10 gpio jtag watchdog 3 timers 2 interrupts aes128 data ram nvm spi sram contr. protocol controller afe power management clock management zero crossing detector pa_in+ pa_in- cl optional external flash memory optional program sram pa_out t x_out rx_in vcc (8-18v) vcca (5v) vddio (3.3/5v) vdd (1.8v) zc_in vdd_pll xin xout
pin connection ST7590 4/24 doc id 18349 rev 1 2 pin connection figure 2. tqfp100 pin connection figure 3. qfn48 (a) pin connection a. the qfn48 package option does not allow the connection wi th an external memory; in this configuration the ST7590 will run the code present in the embedded rom only. !-v 3#,+ 33. 6$$ '.$ -)3/ -)3/?3$! 32!-?! $6$$ 32!-?! 3#,+?3#, 32!-?$ 32!-?$ 32!-?$ 32!-?$ 32!-?$ 32!-?$ 32!-?$ 32!-?$ 32!-?#3. 32!-?7%. 32!-?/%. '0)/ '0)/ '0)/ $6$$ -/3)?48$ -)3/?28$ $6$$ 4234. 4-3 32!-?! 32!-?! 32!-?! 32!-?! 32!-?! 32!-?! 32!-?! 32!-?! 32!-?! 32!-?! 32!-?! 32!-?! 32!-?! 32!-?! 32!-?! $6$$ '.$ 4#+ 4$/ 4$) 2%3%4. .# 6$$ .# .# 8). 8/54 '.$ .# 633! .# .# 6$$?0,, 6##! :#?). 28?). 48?/54 0! ?).?0 0!?).?. #, 6## 6## .# 633 633 0!?/54 0!?/54 .# 6$$?2%'?6 .# 6$$ .# '.$ $6$$ 635"3 '0)/ 6$$ '0)/ 635"3 '0)/ '0)/ '.$ $6$$ 6$$ 6$$?6 '0)/ .# '0)/ .# '0)/ !-v -/3)?48$ -)3/?2 8$ $6$$ 4234. 4-3 4#+ 4$/ 4$) 2%3%4. 6$$ 8). '0)/ 6$$? $6$$ '.$ '0)/ '0)/ '0)/ '0)/ $6$$ 6$$?2%'?6 0!?/54 633 3#,+ 33. 6$$ '.$ -)3/ -/3)?3$! 3#, +?3#, '0)/ '0)/ '0)/ '0)/ '0)/ 8/54 '.$ 633! 6$$?0,, 6##! :#?). 28?). 48?/54 0!?). 0!?). #, 6## '.$
ST7590 pin connection doc id 18349 rev 1 5/24 table 1. pin description name pin type description tqfp qfn sclk0 100 48 digital input spi0 serial clock ssn0 99 47 digital input spii0 slave select (active low) vdd 98 46 power digital power supply (1.8 v) gnd 97 45 power ground miso1 96 44 digital input spi1 data in mosi1_sda 95 43 digital i/o spi1 data out, i2c data in (i2c always selected at boot) sram_a15 94 - digital output external sram address vddio 93 - power 3.3 v - 5 v i/o supply sram_a16 92 - digital output external sram address sclk1_scl 91 42 digital output spi1 serial clock, i2 c serial clock ((i2c alwa ys selected at boot) sram_d0 90 - digital i/o (1) external sram data i/o sram_d1 89 - digital i/o (1) external sram data i/o sram_d2 88 - digital i/o (1) external sram data i/o sram_d3 87 - digital i/o (1) external sram data i/o sram_d4 86 - digital i/o (1) external sram data i/o sram_d5 85 - digital i/o (1) external sram data i/o sram_d6 84 - digital i/o (1) external sram data i/o sram_d7 83 - digital i/o (1) external sram data i/o sram_csn 82 - digital output external sram chip select sram_wen 81 - digital output external sram write enable sram_oen 80 - digital output ext ernal sram output enable gpio0 79 41 digital i/o general purpose i/o gpio1 78 40 digital i/o general purpose i/o gpio2 77 39 digital i/o general purpose i/o vddio 76 - power 3.3 v - 5 v i/o supply gpio3 75 38 digital i/o general purpose i/o n.c 74 - not connected gpio4 73 37 digital i/o general purpose i/o n.c 72 - not connected gpio5 71 36 digital i/o general purpose i/o vdd_12v 70 35 power otp programming voltage (12 v) vdd 69 - power digital power supply (1.8 v) vddio 68 34 power 3.3 v - 5 v i/o supply gnd 67 33 power ground
pin connection ST7590 6/24 doc id 18349 rev 1 gpio6 66 32 digital i/o general purpose i/o gpio7 65 31 digital i/o general purpose i/o vsubs 64 - power analog ground gpio8 63 30 digital i/o general purpose i/o vdd 62 - power digital power supply (1.8 v) gpio9 61 29 digital i/o general purpose i/o vsubs 60 - power substrate ground vddio 59 28 power 3.3 v - 5 v i/o supply gnd 58 - power ground n.c 57 - not connected vdd 56 - power digital power supply (1.8 v) n.c 55 - not connected vdd_reg_1v8 54 27 power 1.8 v digital power supply, internal regulator output n.c 53 - not connected pa_out 52 26 analog output power amplifier output pa_out 51 - analog output power amplifier output vss 50 25 power power ground vss 49 - power power ground n.c 48 - not connected vcc 47 24 power 12 v to 20 v power supply vcc 46 - power 12 v to 20 v power supply cl 45 23 analog input current limiting feedback pa_in_n 44 22 analog input power amplifier inverting input pa_in_p 43 21 analog input power amplifier non-inverting input tx_out 42 20 analog output transmission analog output rx_in 41 19 analog input reception analog input zc_in 40 18 analog input zero crossing detection input vcca 39 17 power 5 v analog supply, internal regulator output vdd_pll 38 16 power 1.8 v pll supply voltage n.c 37 - not connected n.c 36 - not connected vssa 35 15 power analog ground n.c 34 - not connected gnd 33 14 power ground table 1. pin description (continued) name pin type description tqfp qfn
ST7590 pin connection doc id 18349 rev 1 7/24 xout 32 13 analog crystal oscillator output xin 31 12 analog crystal oscillator input n.c 30 - not connected n.c 29 - not connected vdd 28 11 power digital power supply (1.8 v) n.c 27 - not connected resetn 26 10 digital input system reset (active low) tdi 25 9 digital input (1) system/m851ew jtag interface data in tdo 24 8 digital i/o system/m851ew jtag interface data out tck 23 7 digital input system/m851ew jtag interface clock gnd 22 6 power ground vddio 21 - power 3.3 v - 5 v i/o supply sram_a0 20 - digital output external sram address sram_a1 19 - digital output external sram address sram_a2 18 - digital output external sram address sram_a3 17 - digital output external sram address sram_a4 16 - digital output external sram address sram_a5 15 - digital output external sram address sram_a6 14 - digital output external sram address sram_a7 13 - digital output external sram address sram_a8 12 - digital output external sram address sram_a9 11 - digital output external sram address sram_a10 10 - digital output external sram address sram_a11 9 - digital output external sram address sram_a12 8 - digital output external sram address sram_a13 7 - digital output external sram address sram_a14 6 - digital output external sram address tms 5 5 digital input (1) system/m8051ew jtag interface test mode selection trstn 4 4 digital input (1) system/m8051ew jtag interface reset (active low) vddio 3 3 power 3.3 v - 5 v i/o supply miso0_rxd 2 2 digital i/o uart data in, spi0 data out mosi0_txd 1 1 digital i/o uar t data out, spi0 data in 1. active pull up (only in input mode for bi-directional pins) table 1. pin description (continued) name pin type description tqfp qfn
maximum ratings ST7590 8/24 doc id 18349 rev 1 3 maximum ratings 3.1 absolute maximum ratings 3.2 thermal data table 2. absolute maximum ratings symbol parameter value unit min max vcc power supply voltage -0.3 20 v vssa-gnd voltage between vssa and gnd -0.3 0.3 v vddio i/o supply voltage -0.3 5.5 v vi digital input voltage gnd-0.3 vddio+0.3 v vo digital output voltage gnd-0.3 vddio+0.3 v v(pa_in) pa inputs voltage range vss-0.3 vcc+0.3 v v(pa_out) pa_out voltag e range vss-0.3 vcc+0.3 v v(rx_in) rx_in voltage r ange -(vcca+0.3) vcc+0.3 v v(zc_in) zc_in voltage range -(vcca+0.3) vcca+0.3 v v(tx_out, cl) tx_out, cl voltage range vssa-0.3 vcca+0.3 v v(xin) xin voltage range gnd-0.3 vddio+0.3 v i(pa_out) power amplifier output non-repetitive peak current 5 apeak i(pa_out) power amplifier output non-repetitive rms current 1.4 arms t amb operating ambient temperature -40 85 oc t stg storage temperature -50 150 oc v(esd) maximum withstanding voltage range test condition: cdf-aec-q100-002 ?human body model? acceptance criteria: ?normal performance? -2 +2 kv table 3. thermal characteristics (1) 1. typical values. symbol parameter qfn48 tqfp100 unit r thja1 maximum thermal resistance junction-ambient steady state (2) 2. mounted on a 2s pcb. 58 50 c/w r thja2 maximum thermal resistance junction-ambient steady state (3) 3. mounted on a 2s2p pcb, with a dissipating surfac e, connected through vias, on the bottom side of the pcb. 32 25 c/w
maximum ratings ST7590 9/24 doc id 18349 rev 1 3.3 electrical characteristics t a = -40 to +85 c, t j < 125 c, v cc = 18 v unless otherwise specified. table 4. electrical characteristics symbol parameter test cond itions min. typ. max. unit power supply v cc power supply voltage 8 13 18 v i (vcc) rx power supply current - rx mode vcca externally supplied 0.35 0.5 ma i (vcc) tx power supply current - tx mode, no load 22 30 ma v cc uvlo_tl v cc under voltage lock out low threshold 6.1 6.5 6.95 v v cc uvlo_th v cc under voltage lock out high threshold 6.8 7.2 7.5 v v cc uvlo_hyst v cc under voltage lock out hysteresis 250 (1) 700 mv v cca analog supply voltage externally supplied -5% 5 +5% v i (vcca) rx analog supply current - rx mode 56ma i (vcca) tx analog supply current - tx mode v (tx_out) =5 v p-p, no load 8 10 ma v dd digital core supply voltage externally supplied -10% 1.8 +10% v i (vdd) digital core supply current 35 ma i (vdd) digital core supply cu rrent in reset state 8 ma v dd_pll pll supply voltage vdd v i (vdd_pll) pll supply current 0.4 ma v ddio digital i/o supply voltage externally supplied -10% 3.3 or 5 +10% v v ddio uvlo_tl i/o supply voltage under voltage lock out low threshold 2.25 2.4 2.6 v v ddio uvlo_th i/o supply voltage under voltage lock out high threshold 2.45 2.6 2.8 v v ddio uvlo_hyst i/o supply voltage under voltage lock out hysteresis 250 mv
maximum ratings ST7590 10/24 doc id 18349 rev 1 analog front end power amplifier v (pa_out)bias power amplifier output bias voltage - rx mode vcc/2 v gbwp power amplifier gain-bandwidth product 100 mhz i (pa_out)max power amplifier maximum output current 1000 ma rms v (pa_out) tol power amplifier output tolerance (2) -3% 3% v (pa_out) hd2 transmitter output 2 nd harmonic distortion v cc =13 v, v (pa_out) = 7 v p-p, v (pa_out) bias = vcc/2, r load =50 see figure 4 - 71 dbc v (pa_out) hd3 transmitter output 3 rd harmonic distortion -68 dbc v (pa_out) thd transmitter output total harmonic distortion 0.1 % v (pa_out) hd2 transmitter output 2 nd harmonic distortion v cc =18 v, v (pa_out) = 14 v p-p, v (pa_out) bias = vcc/2, r load =50 ? see figure 4 -70 dbc v (pa_out) hd3 transmitter output 3 rd harmonic distortion -60 dbc v (pa_out) thd transmitter output total harmonic distortion 0. 2 % c (pa_in) power amplifier input capacitance pa_in+ vs. v ss (2) 10 pf pa_in- vs. v ss (2) 10 pf psrr power supply rejection ratio dc to 3 khz 100 db 1 khz 93 db 100 khz 70 db c l_th current sense high threshold on cl pin 2.35 v c l_ratio ratio between pa_out and cl output current 80 transmitter v (tx_out) bias transmitter output bias voltage - rx mode vcca/2 v v (tx_out) max transmitter output maximum voltage swing maximum output level, no load v cca = 5 v 4.8 4.95 vcca v p-p txgain transmitter output digital gain range -21 0 db tx_gain tol transmitter output di gital gain tolerance -0.35 0.35 db table 4. electrical characteristics (continued) symbol parameter test cond itions min. typ. max. unit
ST7590 maximum ratings doc id 18349 rev 1 11/24 r (tx_out) transmitter output resistance rx mode 1 k ? v (tx_out) hd2 transmitter output 2 nd harmonic distortion v (tx_out) = 4 vpp (txout)max, no load, f c = 82 khz -67 dbc v (tx_out) hd3 transmitter output 3 rd harmonic distortion -70 dbc v (tx_out) thd transmitter output total harmonic distortion 0.1 % receiver v (rx_in) max receiver input maximum voltage v cc = 18 v 16 v p-p v (rx_in) bias receiver input bias voltage 2.5 v z (rx_in) receiver input impedance 10 k ? pga_min pga minimum gain -18 db pga_max pga maximum gain 30 db oscillator v (xin) oscillator input voltage swing clock frequency supplied externally 1.8 vddio v p-p v (xin) th oscillator input voltage threshold 0.8 0.9 1 v v (xin) f osc crystal oscillator frequency 8mhz f(xin) tol external quartz crystal frequency tolerance -150 150 ppm esr external quartz crystal esr value 100 c l external quartz crystal load capacitance 16 pf temperature sensor t_th 1 temperature threshold 1 (2) 63 70 77 c t_th 2 temperature threshold 2 (2) 90 100 110 c t_th 3 temperature threshold 3 (2) 112 125 138 c t_th 4 temperature threshold 4 (2) 153 170 187 c zero crossing comparator v (zc_in) max zero crossing detection input voltage range 10 v p-p table 4. electrical characteristics (continued) symbol parameter test cond itions min. typ. max. unit
maximum ratings ST7590 12/24 doc id 18349 rev 1 v (zc_in) tl zero crossing detection input low threshold -44 -32 -17 mv v (zc_in) th zero crossing detection input high threshold 26 41 56 mv v (zc_in) hyst zero crossing detection input hysteresis 73 mv digital section digital i/o r pull-up internal pull-up resistors vddio = 3.3 v 66 k ? vddio = 5 v 41 v ih high logic level input voltage 0.65* vddio vddio +0.3 v v il low logic level input voltage -0.3 0.35* vddio v v oh high logic level output voltage i oh = -4 ma vddio -0.4 v v ol low logic level output voltage i ol = 4 ma 0.4 v uart interface data bits 8bits stop bits 1bits parity bits 0bits baud rate -1.5% 57600 +1.5% baud -1.5% 38400 +1.5% baud -1.5% 19200 +1.5% baud -1.5% 9600 +1.5% baud reset and power on t resetn minimum valid reset pulse duration 1 s t startup start-up time at power on or after a reset event (3) 35 60 ms 1. referred to t a = -40c 2. this parameter does not include the tolerance of external components 3. referred to ic start up, uploading code from external nvm and its execution from external ram may require some second. table 4. electrical characteristics (continued) symbol parameter test cond itions min. typ. max. unit
ST7590 maximum ratings doc id 18349 rev 1 13/24 figure 4. power amplifier test circuit c1 10n c2 1u r3 330k r4 330k r_load 50r r1 4k r2 15k vcc vcc signal source pa_in_p pa_in_n pa_out
analog front end (afe) ST7590 14/24 doc id 18349 rev 1 4 analog front end (afe) 4.1 reception path figure 5 shows the block diagram of the ST7590 input receiving path. the reception afe main blocks are a wide input range analog pga (programmable gain amplifier) and the adc (analog to digital converter). figure 5. reception path block diagram the pga is controlled by a loop algorithm that detects the amplifier output signal amplitude and adapts the gain of the amplifier in order to have the optimum input voltage range for the adc. the pga gain ranges from -18 db up to 30 db (typical), with steps of 6 db (typical), as described in table 5. table 5. pga gain table pga code pga gain (typ ical) rx_in max range [db] [v p-p] 0-18 16 1-12 8 2-6 4 30 2 46 1 5 12 0.500 6 18 0.250 7 24 0.125 8 30 0.0625 !-v 28!&% "0& !$# 28?). "0& "0& !$# !$# 0'! 0'!
ST7590 analog front end (afe) doc id 18349 rev 1 15/24 4.2 transmission path figure 6 shows the transmission path block diagram. it is mainly based on a digital to analog converter (dac), capable to generate a very linear signal up to its full scale output. a gain control block before the dac gives the possibilit y to scale down the output signal to match the desired transmission level. figure 6. transmission path block diagram according to prime specifications the output level can be set on a 8-step logarithmic scale between a maximum output level (mol) and a minimum output level (mol - 21db), with steps of 3db (typical). the maximum level corresponds to the tx_out full range. 4.3 power amplifier the integrated power amplifier is characterized by very high linearity, required to comply with the different international regulations (cenelec, fcc etc.) limiting the spurious conducted emissions on the mains, and a current capability of 1arms (typical) that allows the amplifier driving even very low impedance points of the network. all pins of the power amplifier are accessible, making it possible to build an active filter network to increase the linearity of the output signal. 4.4 thermal shutdown and temperature control the ST7590 performs an automatic shutdown of the power amplifier circuitry when the internal temperature exceeds 170 c. after a thermal shutdown event, the temperature must get below 125 c before the ST7590 power amplifier comes back to operation. moreover a digital thermometer is embedded to identify the internal temperature among four zones, as indicated in ta b l e 6 . !-v 48!&% $!# 'ain #ontrol 48?/54 48'!). "0& "0& table 6. temperature zones temperature zone temperature range (typ.) 1 t < t_th 1 2t_th 1 < t < t_th 2 3t_th 2 < t < t_th 3 4 t > t_th 3
analog front end (afe) ST7590 16/24 doc id 18349 rev 1 4.5 zero-crossing detector the ST7590 embeds an analog comparator with hysteresis, used for zero-crossing detection. information about zero crossing events is managed as specified in prime protocol specifications. 4.6 one time programmable (otp) memory array ST7590 comes with an embedded 64 bit otp array. this otp memory is used to store hardware trimming values and the unique identifier eui48, used for unique addressing in prime mac protocol. otp array is composed of 4 16 bit words, indexed from 0 to 3, where the first (index 0) contains hardware trimming values, while the others contain the eui48 address as specified in ta b l e 7 . 4.7 power management figure 7 shows the power supply structure for the ST7590. the ST7590 operates from two external supply voltages: vcc (8 to 18 v) as the main power supply; vddio (3.3 or 5 v) for the i/o and digital sections. two internal linear regulators provide the remaining required voltages: 5 v regulator (used by the analog front end blocks), generated from the vcc voltage and connected to the vcca pin; 1.8 v regulator (required for the dsp and microcontroller cores, the digital blocks, the pll and the oscillator), generated from th e vddio voltage and connected to the vdd_reg_1v8 pin. all the supply voltages must be properly filtered, to their respective ground, using external capacitors close to each supply pin (see figure 7 ). note: the internal regulators connected to vd d_reg_1v8 and vcca are not designed to supply external circuitry; their output is externa lly accessible for filtering purpose only. table 7. otp memory array index lsb msb 0 reserved ? hardware trimming 1 eui48[0..7] eui48[8..15] 2 eui48[16..23] eui48[24..31] 3 eui48[32..39] eui48[40..47]
ST7590 analog front end (afe) doc id 18349 rev 1 17/24 figure 7. power supply internal scheme 4.8 clock management the main clock source is an 8 mhz crystal co nnected to the internal oscillator through xin and xout pins. both xin and xout pins have a 32 pf integrated capacitor, in order to drive a crystal having a load capacitance of 16 pf with no additional components. alternatively, an 8 mhz external clock can be directly supplied to xin pin, leaving xout floating. a pll internally connected to the output of the oscillator generates the internal clocks needed by the digital part. ldo vcc vss vcca vssa ldo vddio gnd vdd vssa vdd_pll 8-18v external supply 3.3 or 5v external supply power amplifier afe digital interfaces digital core internal pll
application information ST7590 18/24 doc id 18349 rev 1 5 application information figure 8. tqfp100 128 kb external memory application example figure 9. qfn48 application example emc filter switched mode power supply power line interface zero crossing conditioning power amplifier feedback host controller serial non volatile memory parallel asynchronous ram memory ST7590 tqfp100 rxd txd resetn gpio6 sclk1 miso1 mosi1 gpio1 sram_a0..16 sram_d0..7 sram_oen sram_wen sram_csn vcc vddio pa_in+ pa_in- tx_out pa_out rx_in zc_in phase neutral emc filter switched mode power supply power line interface zero crossing conditioning power amplifier feedback host controller ST7590 qfn48 rxd txd resetn gpio6 vcc vddio pa_in+ pa_in- tx_out pa_out rx_in zc_in phase neutral
ST7590 package mechanical data doc id 18349 rev 1 19/24 6 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack is an st trademark. table 8. tqfp 100 package mechanical data dim. (mm) min. typ. max. a 1.2 a1 0.05 0.15 a2 0.95 1 1.05 b 0.17 0.22 0.27 c 0.09 0.2 d 15.8 16 16.2 d1 13.8 14 14.2 d2 5.00 5.50 d3 12 e 15.8 16 16.2 e1 13.8 14 14.2 e2 5.00 5.50 e3 12 e 0.5 l 0.45 0.6 0.75 l1 1 k 0 3.5 7 ccc 0.08
package mechanical data ST7590 20/24 doc id 18349 rev 1 figure 10. tqfp 100 package outline
ST7590 package mechanical data doc id 18349 rev 1 21/24 table 9. qfn-48 (7 x 7 mm) package mechanical data dim. (mm) min. typ. max. a 0.80 0.90 1.00 a1 0.02 0.05 a2 0.65 1.00 a3 0.25 b 0.18 0.23 0.30 d 6.85 7.00 7.15 d2 4.95 5.10 5.25 e 6.85 7.00 7.15 e2 4.95 5.10 5.25 e 0.45 0.50 0.55 l 0.30 0.40 0.50 ddd 0.08
package mechanical data ST7590 22/24 doc id 18349 rev 1 figure 11. qfn-48 (7 x 7 mm) package outline
ST7590 revision history doc id 18349 rev 1 23/24 7 revision history table 10. document revision history date revision changes 19-oct-2011 1 initial release
ST7590 24/24 doc id 18349 rev 1 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by two authorized st representatives, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2011 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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